The present invention relates to power devices including power metal-oxide-semiconductor field effect devices or transistors (“MOSFETs”) and insulated gate bipolar transistors (“IGBTs”).
The power semiconductor devices include a MOSFET that is a majority carrier device and an IGBT that functionally integrates a MOSFET and Bipolar Junction Transistor. There are four types of MOSFETs: (1) n-channel device operating in enhancement mode, (2) n-channel device operating in depletion mode, (3) p-channel device operating in enhancement mode, and (4) p-channel device operating in depletion mode. Most of commercially available Power MOSFETs are n-channel devices because higher carrier mobility of electrons provides lower on-state losses for n-channel MOSFETs. Examples of n-channel devices will be discussed below though extension to p-channel devices is possible.
Currently most common Power MOSFETs are manufactured as either a planar double diffused MOSFET (“DMOS”) or a trench MOSFET. The DMOS devices and trench MOSFETs are distinguished by their respective gate structures and channel geometry. Channel is parallel to the plane of substrate for DMOS transistors. Trench MOSFET have a channel which is vertical to respect of the plane of substrate.
As shown in FIG. 1, a DMOS cell 30 has a planar gate structure that is provided on the substrate. The DMOS cell 30 includes a polysilicon gate 10 that is substantially planar and parallel to the top surface of a semiconductor substrate 31. Although the DMOS transistor generally includes a plurality of gates, only one gate is shown for illustrative simplicity.
In case of N-channel DMOS transistor the substrate is an n− type semiconductor material and includes an upper layer 20 that is n− layer and a lower layer 21 that is n+ layer. Generally the upper n− layer 20 has a lower doping concentration than the lower layer. A gate electrode 12 is connected to the polysilicon gate 10. A film of gate dielectric 24, typically-silicon oxide, provided below the gate 10 is parallel to the top surface and has a planar structure. A JFET conduction area 23 between p-wells 16 is formed below the gate 10. A plurality of source regions 15 is provided on the edges of the gate 10. The source regions are n− type regions and defined within the p-wells 16. A drain electrode 22 is formed on a bottom surface of the substrate 31. Accordingly, electrons flow vertically from the source to drain regions when positive voltage is applied to the gate electrode 12 with respect to source electrode 13.
FIG. 2 illustrates a trench power MOS transistor 100 including a polysilicon gate 119 that is formed within a trench 111. Accordingly, the gate 119 is not planar in respect to the top surface of a semiconductor substrate 102. The substrate includes an n− upper layer 120 and an n+ lower layer. A p-well 126 is formed at upper portion of the n− layer 120.
The trench includes substantially vertical side walls 130 etched into the substrate. Accordingly, the gate 119 has a significant vertical portion extending into the substrate. Generally, a bottom of the trench penetrates the p-well 126 and extends into a layer underneath, i.e., the n− layer 120.
Power devices are generally characterized by breakdown voltage (“BV”) ratings to indicate their normal voltage range of operations. The BV of conventional power device is influences by several factors: (1) the curvature of the p-wells 16 of the transistors (the greater the curvature, the lower the BV of the device); (2) the thickness and resistivity of the n− layer 20 (the lower thickness or resistivity the lower BV of the device); (3) depth of p-well 16 (for a given n− region thickness, the deeper the p-well, the lower the BV since the deeper p-well reduces the net n− layer thickness). As illustrated in FIG. 1, the net thickness of the n− layer 20 is defined as a distance t1 from a bottom surface of the p-well 16 to a bottom surface of the n− layer 20 in FIG. 1. In FIG. 2, the net thickness of n− layer 120 is a distance from a bottom of the gate structure to a bottom of the n− layer. The depth of the p-well 16 is defined as a distance p1 from a top surface of the substrate to a bottom surface of the p-well.
In case of the planar DMOS transistor, the BV of the device in active area is sufficiently lower than BV of a planar p-n junction formed in the same n− layer. Relative reduction of BV is due to the curvature of the p-n junction 50 and the equi-potential lines 48, as illustrated in FIG. 3. The equi-potential lines 48 describe the potential distribution in the devices under reverse voltage bias in its off state. The shallower the p-wells the higher the curvature of p-n-junction, the higher the concentration of electrical field associated with p-n junction curvature the lower the BV.
In addition, the planar DMOS transistors are affected by a “neck” problem due to the curved p-wells. That is, a narrow current path or “neck” is created under the gate area 23 in the n-region between adjacent p-wells (FIGS. 1 and 3). This neck causes formation of a constricted current flow region for the electrons when the transistor is turned on. This constricted region is also referred to as the “JFET” region because of modulation of resistance of this area by the potential of p-well (pinch-off). This region adds to the on resistance (Ron) of the power DMOS transistors. A “boxed” region 60 in FIG. 3 represents the neck region that contributes to the increase of Ron. When the planar DMOS device is turned on, the current has to go through this neck region, thereby reducing the efficiency of the device. As the voltage ratings of the device increases above a certain level (e.g., about 150V), this increase in Ron becomes a more serious issue.
Trench gate MOS transistors are not affected by “neck” problem. P-n junction of the p-well 126 and n− layer 120 (FIG. 2) is substantially flat, so there is no electrical field concentration and reduction of the BV due to p-n junction curvature. Referring again to FIG. 2, a bottom portion 131 of the gate that penetrates through p-well 126 creates a sharp geometry in the n-region 120. Higher electric fields are formed thereon, thereby reducing the BV of the device. A method of forming trench power MOSFETs as V-groove MOS is described in “MOSPOWER Application Handbook,” by Rudy Severns, 1984, Chapter 2.5; and K. Lisiak and J. Berger, “Optimization of Nonplanar Power MOS Transistors,” IEEE Transaction Electron Devices Vol. ED-25, 1978 pp. 1229–1234. Furthermore, the net epi thickness is reduced to a thickness t4 under the trench gate from a thickness t3 due to extension of the bottom portion 131 into the n− layer 120, which increases the electric field at that location and reduces the BV.
The shape of the trench which creates a protrusion with a sharp curvature or edges also leads to increased electric fields, as depicted by the curvature of equi-potential lines 150 in FIG. 2. The equi-potential lines are compressed at a region 152 below the trench since the same potential lines occupy a thinner epi region, thereby resulting in increased electric fields and reduced BV.
Furthermore, when the device is in a blocking voltage state, the penetration of the trench 111 into the epi region 120 forces parts of the electric fields to be in a portion of the gate oxide 124 under the gate on the tip of the bottom portion 131 of the trench 111. This extra field in the gate oxide exposes the device to gate oxide rupture failures during high voltage operations and high power switching applications. As a result, the trench MOS technology has found limited use in high voltage power MOS applications, e.g., at about 200V and above.